First x86 to introduce 256 bit AVX instruction set and implementation of YMM registers. Formerly called Gesher but renamed in 2007. Sandy Bridge 32 nm microarchitecture, released January 9, 2011. Westmere: 32 nm shrink of the Nehalem microarchitecture with several new features.Added important powerful new instructions, SSE4.2. Incorporates the memory controller into the CPU die. Nehalem released November 17, 2008, built on a 45 nm process and used in the Core i7, Core i5, Core i3 microprocessors. Penryn: 45 nm shrink of the Core microarchitecture with larger cache, higher FSB and clock speeds, SSE4.1 instructions, support for XOP and F/SAVE and F/STORE instructions, enhanced register alias table and larger integer register file.64-bit ( x86-64) Core reengineered P6-based microarchitecture used in Intel Core 2 and Xeon microprocessors, built on a 65 nm process, supporting x86-64 level SSE instruction and macro-op fusion and enhanced micro-op fusion with a wider front end and decoder, larger out-of-order core and renamed register, support loop stream detector and large shadow register file. Later revisions were the first to feature Intel's x86-64 architecture, enhanced branch prediction and trace cache, and eventually support was added for the NX (No eXecute) bit to implement executable-space protection. The Prescott was a major architectural revision. Used in Pentium 4, Pentium D, and some Xeon microprocessors. NetBurst commonly referred to as P7 although its internal name was P68 (P7 was used for Itanium). Enhanced Pentium M: updated, dual core version of the Pentium M microarchitecture used in the first Intel Core microprocessors, first x86 to have shadow register architecture and speed step technology.Pentium M: updated version of Pentium III's P6 microarchitecture designed from the ground up for mobile computing and first x86 to support micro-op fusion and smart cache.Added 36-bit physical memory addressing, "Physical Address Extension (PAE)". Some important new instructions, including conditional moves, which allow the avoidance of costly branch instructions. First x86 processor to support SIMD instruction with XMM register implemented, RISC μop decode scheme, integrated register renaming and out-of-order execution. P6 used in Pentium Pro, Pentium II, Pentium II Xeon, Pentium III, and Pentium III Xeon microprocessors. P5 original Pentium microprocessors, first x86 processor with super-scalar architecture and branch prediction. i486 Intel's second generation of 32-bit x86 processors, introduced built-in floating point unit (FPU), 8 KB on-chip L1 cache, and pipelining. Many additional powerful and valuable new instructions. Introduced paging on top of segmentation which is the most commonly used memory protection technology in modern operating systems ever since. Included instructions relating to protected mode. Performance improved by a factor of 3 to 4 over 8086. 286 first x86 processor with protected mode including segmentation based virtual memory management. The 80188 was a version with an 8-bit bus. A small number of additional instructions. 186 included a DMA controller, interrupt controller, timers, and chip select logic. 8088 version, with an 8-bit bus, used in the original IBM Personal Computer. Note: Atom/Power efficient microarchitectures are in Italicġ6-bit 8086 first x86 processor initially a temporary substitute for the iAPX 432 to compete with Motorola, Zilog, and National Semiconductor and to top the successful Z80. X86 microarchitectures x86 microarchitectures Additional details can be found in Intel's Tick–tock model and Process–architecture–optimization model. The following is a partial list of Intel CPU microarchitectures. This list is incomplete you can help by adding missing items.
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